1. Field of the Invention
This disclosure relates to semiconductor technology, and more particularly, to a semiconductor device and manufacturing method for the same.
2. Description of the Related Art
As semiconductor processing technology advances, the critical dimension (CD) of a semiconductor device continuously scales down. In such case, requirements for semiconductor manufacturing processes have become more stringent.
Taking a fin field effect transistor (FinFET) as an example, as the CD of the semiconductor device scales down, it is almost impossible to form a desired dimension of the fin, e.g., a width of the fin, by patterning with lithography. In such case, typically, a spacer image transfer (SIT) process is used to achieve a fin having such a small dimension.
In the SIT process, for example, first, spacers are formed adjacent to mandrels. After mandrels are removed, a semiconductor layer in a substrate such as a SOI substrate is etched using the spacers as a mask and then, fins are formed. In this process, the width of the spacer defines the width of the fin.
However, in the prior art, how to prevent fin collapse/undesired remove during manufacturing becomes an importance problem, when the CD of fin continuously scales down.
FIG. 1A illustrates a schematic configuration for a prior art FinFET. As an example, a pair of fins is shown. However, those skilled in the art may appreciate that one or more fins can be included in the FinFET. In this example, a semiconductor-on-insulator (SOI) substrate is taken as an example. As shown in FIG. 1A, the semiconductor device 10 comprises a base substrate 100, an insulator layer 102 disposed on the base substrate 100, a patterned semiconductor layer 104 formed on the insulator layer 102, and a patterned hard mask layer 106 formed on the patterned semiconductor layer 104. The semiconductor layer 104 and the hard mask layer 106 form a fin structure. As shown, in this example, the fin structure is disposed on the insulator layer of the SOI substrate. As the thickness of the fin structure continuously decreases, the fin structure tends to collapse and/or be undesirably removed during subsequent manufacturing processes. As a result, the yield of the semiconductor device may be adversely affected.
FIG. 1B illustrates a schematic configuration for another prior art FinFET. The shown semiconductor device 10′ differs from the semiconductor device 10 shown in FIG. 1A in that the hard mask layer 106 is removed. In such case, the semiconductor layer 104 forms the fin structure. Likewise, as the thickness of the fin structure continuously decreases, the fin structure tends to collapse and/or be undesirably removed during subsequent manufacturing processes. As a result, the yield of the semiconductor device may be adversely affected.
Therefore, there is a continuous demand in the art for an improved semiconductor device and a manufacturing method therefor.